Microcoded Reconfigurable Embedded Processors

I n this dissertation, we present a new approach in embedded processor design that entails the augmentation of a programmable processor with reconfigurable hardware. To this end, we re-introduce and extend traditional microcode concepts to emulate the configuration process of the augmented reconfigurable hardware in addition to the emulation of the execution process on both fixed and reconfigurable hardware. The resulting microcode is referred to as ρμ-code. More specifically, we extend the functionality of the traditional control store to also facilitate the storage of reconfiguration microcode next to execution microcode (i.e., the traditional microcode). The storage is organized such that it provides storage for frequently used and less frequently used reconfiguration microcode in the fixed and pageable storage within the ρ-Control Store, respectively. Furthermore, to hide the reconfiguration time, we have conceptually separated the support for reconfigurable hardware into two distinct phases. First, in the set phase the reconfigurable hardware is configured in order to support the targeted operations. Second, in the execute phase the actual execution of the targeted operations is being performed. This separation and the introduction of specialized registers (with proper move instructions) allow a one-time architectural (instruction set) extension to support arbitrary reconfigurations. In order to show the performance potential of our approach, we focused on multimedia processing. We established a reference case by gathering simulation results when running multimedia benchmarks on a cycle-accurate simulator. Subsequently, we modified both the simulator and the benchmarks in order to reflect our approach and again gathered simulation results. In addition, we have implemented several well-known multimedia operations in VHDL and synthesized them in order to gain insight into their possible clock speeds. The obtained results show that the number of execution clock cycles can be roughly decreased by 30% and the number of executed instructions is decreased by about 66%.